3D Stacked IC Publications

1. Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, and Sung Kyu Lim, "Wire Congestion And Thermal Aware 3D Global Placement," IEEE/ACM Asia South Pacific Design Automation Conference, p1131-1134, 2005. (pdf)
2. Jacob Minz, Sung Kyu Lim, and Cheng-Kok Koh, "3D Module Placement for Congestion and Power Noise Reduction," ACM Great Lake Symposium on VLSI, p458-461, 2005. (pdf)
3. Jacob Minz, Eric Wong, and Sung Kyu Lim, "Reliability-aware Floorplanning for 3D Circuits," in IEEE International SOC Conference, 2005. (pdf)
4. Kiran Puttaswamy and Gabriel H. Loh, "Implementing Caches in a 3D Technology for High Performance Processors" IEEE International Conference on Computer Design, pp. 525-532, 2005. (pdf)
5. Eric Wong and Sung Kyu Lim, "3D Floorplanning with Thermal Vias," in Design, Automation and Test in Europe, 2006.
6. Kiran Puttaswamy and Gabriel H. Loh, "Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology," IEEE International Symposium on VLSI, pp. 384-389, 2006. (pdf)
7. Kiran Puttaswamy and Gabriel H. Loh, "The Impact of 3-Dimenstional Integration on the Design of Arithmetic Units," IEEE International Symposium on Circuits and Systems, pp. 4951-4954, 2006. (pdf)
8. Kiran Puttaswamy and Gabriel H. Loh, "Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor," ACM/IEEE Great Lakes Symposium on VLSI, 19-24, 2006. (pdf)
9. Kiran Puttaswamy and Gabriel H. Loh, "Dynamic Instruction Schedulers in a 3-Dimensional Integration Technology," ACM/IEEE Great Lakes Symposium on VLSI, 153-158, 2006. (pdf)
10. Yuan Xie, Gabriel H. Loh, Bryan Black and Kerry Bernstein, "Design Space Exploration for 3D Architectures," ACM Journal on Emerging Technologies in Computing Systems, vol.2(2), pp. 65-103, 2006. (pdf)
11. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," in IEEE International Conference on Computer Aided Design, 2006.
12. Bryan Black, Murali M. Annavaram, Edward Brekelbaum, John DeVale, Gabriel H. Loh, Lei Jiang, Don McCauley, Pat Morrow, Don Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb, "Die Stacking (3D) Microarchitecture," in IEEE International Symposium on Microarchitecture, 469-479, 2006. (pdf)
13. Kiran Puttaswamy, Gabriel H. Loh, "Thermal Herding: Microarchitecture Techniques for Controlling HotSpots in High-Performance 3D-Integrated Processors," in IEEE International Symposium on High-Performance Computer Architecture, 193-204, 2007. (pdf)
14. Kiran Puttaswamy, Gabriel H. Loh, "Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors," in ACM Design Automation Conference, 2007. (pdf)
15. Gabriel H. Loh, Yuan Xie, Bryan Black, "Processor Design in Three-Dimensional Die-Stacking Technologies," to appear in IEEE Micro, Vol. 27(3), May-June, 2007.
16. Dean Lewis, Hsien-Hsin S. Lee, "A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors," to appear in the IEEE International Test Conference, 2007.
17. Mohit Pathak, Sung Kyu Lim, "Thermal-aware Steiner Routing for 3D Stacked ICs," to appear in the IEEE International Conference on Computer-Aided Design, 2007.
18. Eric Wong and Sung Kyu Lim, "Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs", to appear in IEEE International Conference on Computer Design, 2007.
19. Mrinmoy Ghosh and Hsien-Hsin S. Lee, "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs." To appear in Proceedings of the 40th ACM/IEEE International Symposium on Microarchitecture, Chicago, IL, December, 2007.
20. Jacob Minz, Xin Zhao, and Sung Kyu Lim, "Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations", to appear in IEEE/ACM Asia South Pacific Design Automation Conference, 2008.
21. Gabriel H. Loh, "A Modular 3D Processor for Flexible Product Design and Technology Migration", to appear in ACM International Conference on Computing Frontiers, May, 2008.
22. Gabriel H. Loh, "3D-Stacked Memory Architectures for Multi-Core Processors", to appear in ACM International Symposium on Computer Architecture, June, 2008.