Welcome to the Georgia Tech 3D Integration Research website! Our mission is to provide insights as well as automated tools, microarchitectures and circuits to design highly optimized 3D processors, 3D mixed-signal System-On-Chips, and 3D mixed-signal System-On-Packages. We achieve this goal by tackling the 3D design issues at multiple levels of abstractions: microarchitecture, circuit, packaging.

PEOPLE

PROJECTS

• Co-Optimization and Limit Study of Thermal, Power, Clock, and Signal Distribution Networks in 3D ICs (funded by SRC/IFC)
• Microarchitecture Design for 3D Processors (funded by SRC FCRP/C2S2)
• Physical Design for 3D System-on-Package (funded by NSF)
• Physical Design for 3D Stacked ICs (funded by NSF)
• Computer Architecture Foundations for 3D-Integrated High-Performance Microprocessors (funded by NSF)
• Parallel-on-Demand - A Broad Purpose 3D-Integrated Performance Acceleration Layer for General Purpose Processors (funded by NSF)

PUBLICATIONS

• 3D Stacked ICs
• Microarchitectural Floorplanning
• 3D Packaging

NEWS ARTICLES

• IBM Cools 3D Chips with H2O
• MetaRAM Uses 3D Chip-stacking Technology
• Sematech - Economics May Drive Push to 3D ICs
• 3D Integration Tour: Are TSVs the Future of Advanced Packaging?
• IBM readies direct chip-to-chip links
• New dimensions in performance
• Sematech targets infrastructure for 3-D chips
• SI Weekly Special Report: 3-D Integration
• Future Package Technologies for Wireless Communication Systems
• New 3-D Chip Interconnect Technology
• 3-D Integration Enables 1 Gb Memory

10 August 2007: We have a new funding from MARCO IFC for "Design Space Exploration of Package-aware 3D Stacked ICs".

22 July 2007: ECE MS Student Eric Wong's paper "Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs" was accepted for publication in the IEEE International Conference on Computer Design, 2007.

28 June 2007: ECE PhD Student Mohit Pathak's paper "Thermal-aware Steiner Routing for 3D Stacked ICs" was accepted for publication in the IEEE Internation Conference on Computer-Aided Design, to be held in November, 2007.

06 June 2007: Profs. Lee, Lim and Loh's triple NSF CAREER awards featured on SRC's FCRP website.

25 May 2007: ECE PhD Student Dean Lewis' paper "A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors" was accepted for publication in the IEEE Internation Test Conference, to be held in October, 2007.

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