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Welcome to the Georgia Tech 3D Integration Research website! Our mission is
to provide insights as well as automated tools, microarchitectures and
circuits to design highly optimized 3D processors, 3D mixed-signal
System-On-Chips, and 3D mixed-signal System-On-Packages. We achieve this goal
by tackling the 3D design issues at multiple levels of abstractions:
microarchitecture, circuit, packaging.
10 August 2007: We have a new funding from MARCO IFC for "Design Space Exploration of Package-aware 3D Stacked ICs".
22 July 2007: ECE MS Student Eric Wong's paper "Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs" was accepted for publication in the IEEE International Conference on Computer Design, 2007.
28 June 2007: ECE PhD Student Mohit Pathak's paper "Thermal-aware Steiner Routing for 3D Stacked ICs" was accepted for publication in the IEEE Internation Conference on Computer-Aided Design, to be held in November, 2007.
06 June 2007: Profs. Lee, Lim and Loh's triple NSF CAREER awards featured on SRC's FCRP website.
25 May 2007: ECE PhD Student Dean Lewis' paper "A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors" was accepted for publication in the IEEE Internation Test Conference, to be held in October, 2007.
GT 3D Integration Research|
Georgia Institute of Technology
Last modified 30 May '08